MS8000
+
  • MS8000

Product Introduction

In an era where the demand for intelligent and new energy devices is growing, iterative processes bring about the need for more cost-effective, stable, and reliable ATE to achieve more efficient mass production of complex SoC devices with higher density.

Macrotest's latest generation SoC testing system MS8000 adopts an integrated test head architecture, high-speed system bus, and system-level boards, providing higher resource density and ultra-high parallel testing capabilities. The MS8000 allows for various high-end functions at a lower cost to adapt to new SoC testing trends.

The MS8000 will become one of the most competitive products in the local and global SoC testing market by providing optimized cost-performance solutions.

 

Applications

Microprocessors, FPGA, memory (EEPROM, SRAM, Flash), MEMS (ToF), PMIC, Internet of Things (IoT), audio and mixed-signal devices, LED drivers

 

Features

Up to 200MHz, 400Mbps data rate

Up to 1536 digital I/O channels

Up to 768 sites for parallel testing

8M acquisition memory per pin

System-level boards:

*DPO16 option: integrates 16 VI sources

*CTO and DSCU options: for mixed-signal testing

*Memory test unit and simplified memory vector generator (SMPG)

*SCAN option: maximum 4G depth/chain

*Maximum 512M vector storage depth

*Independent test processor for each board

Optional multi-core test processor

True parallel trim and match

PMU, dynamic load, TMU, free-running clock, and protocol-level testing for each pin

Memory test options for embedded memory

Multiple VI options: 60V high voltage VI and high-density VI

Visual ATE software for development, maintenance, and production

Data analysis tools, digital/analog waveform tools, vector tools, debugging tools, etc.

Vector code compatible with J7XX

STDF tools

Vector programming (POP)

Vector/test program converter

Note: Lines marked with (*) are related to digital channel board options.

 

Advantages

Independently developed by a local team.

High performance comparable to international mainstream platforms.

Competitive architecture (high-speed bus/system-level boards/integrated test head) helps reduce testing costs.

Multiple technological innovations in test processors and parallel testing (protocol-level testing/memory vector generator/multi-clock domains) and multi-core processors improve efficiency.

 

Specifications

Item

Specifications

Test Rate

200MHz, 400Mbps

Digital I/O Channels

768 pins (up to 1536 pins)

VI Source Channels

More than 384 channels at most

Parallel Testing Capability

Up to 768 DUTs

Vector Storage Depth

Optional maximum 512M

EPA

± 500ps

Per Pin Resource Architecture

PPMU, time test unit, dynamic load, free-running clock, protocol-level testing

Digital Board (DCBU, system-level board)

Digital Channel Board

64 channels or 128 channels

Driver (VIL/VIH-2V~+6V)

Per Pin

Comparator (VOL/VOH -2V~+ 6V)

Per Pin

High Voltage Pin Driver (-1.5V~+15.5V)

1 channel per 8 pins (optional: 1 channel per 2 pins)

PPMU (-2V~+ 6V, ± 50 mA)

Per Pin (FIMV/FVMI)

Programmable Dynamic Load (±24 mA)

Per Pin

PTMU (Time/Frequency Measurement Unit: 1GHz sampling rate)

Per Pin

SCAN (maximum 4G depth)

Up to 32 scan chains

Digital Signal IO

Up to 8 output and acquisition engines

Protocol-level Testing

Output 64 bits, input 32 bits

Device Power on Digital Board (DCBU, system-level board)

DPS (BUVI Rider, -2~+12V, ±512mA)

8 channels per board, can be paralleled

BPMU (same specifications as DPS, can be used as DPS)

8 channels per board

Memory test unit on digital board (DCBU, system-level board)

Storage vector generator

X=24, Y=24, Z=10, D=36

Converter test option on digital board (DCBU, system-level board)

 

Arbitrary waveform generator

2 AWG/Board, 20 bits

Digitizer

2 DIG/Board, 16 bits

Reference voltage

2 Vref/Board, 0V~+ 6V

High voltage VI board (HDVI12)

-40 ~ +60V, maximum 1A

12 channels per board

High density power board (DPS64)

-2 ~ +12V, maximum ± 512mA

64 channels per board, can be paralleled

Software

 

Windows environment

Version above Windows 10

Programming language

C++

Test system software

Self-developed software platform: Visual ATE Mix

Test vector conversion tool

Supports J750, 3380, S200 etc.

System and dimensions

Power consumption

Maximum 8KW

Test head dimensions

13 slots, L720*W580*H510 mm

 

Software platform - Visual ATE Mix

The newly designed test software platform Visual ATE Mix includes development, maintenance, and mass production environments, and integrates rich development and debugging tools, which can help test engineers efficiently and quickly develop, debug, and release test programs according to test specifications, ultimately shortening the time to market for customer products.

Visual ATE Mix is the universal software platform for all Macrotest IC testers, including SoC testers and analog testers.

IDE

Visual ATE Mix IDE features a modern visual interface, supporting form filling, code, and template programming.

OI

The Visual ATE Mix operation interface provides customers with a process interface for starting production and integrates real-time monitoring and dynamic PAT, which can be used for automotive device testing.

MI

The Visual ATE Mix maintenance interface is used for visual calibration, inspection, and verification. Users can obtain system and device information from the MI interface.

Tools

Visual ATE Mix provides various debugging tools to accelerate program development and import time.

Feature testing tools

Keywords

MS8000

MS8000
+
  • MS8000

MS8000

In an era where the demand for intelligent and new energy devices is growing, iterative processes bring about the need for more cost-effective, stable, and reliable ATE to achieve more efficient large-scale production of complex SoC devices with higher density. Macrotest's latest generation SoC testing system, the MS8000, features an integrated test head architecture, high-speed system bus, and system-level circuit boards, providing higher resource density and ultra-high parallel testing capabilities. The MS8000 allows for the acquisition of various high-end functions at a lower cost, adapting to new trends in SoC testing. The MS8000 aims to become one of the most competitive products in the local and global SoC testing market by offering optimized cost-performance solutions.


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